Question about 1 port ram

128 data at 32 bit is only 4k, using only about 20% of the ram.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY memory IS
    PORT
    (
        clock        : IN STD_LOGIC  := '1';
        data        : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        rdaddress        : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
        wraddress        : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
        wren        : IN STD_LOGIC  := '0';
        q        : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
    );
END memory;
ARCHITECTURE SYN OF memory IS
    SIGNAL sub_wire0    : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
    q    <= sub_wire0(31 DOWNTO 0);
    altsyncram_component : altsyncram
    GENERIC MAP (
        address_aclr_b => "NONE",
        address_reg_b => "CLOCK0",
        clock_enable_input_a => "BYPASS",
        clock_enable_input_b => "BYPASS",
        clock_enable_output_b => "BYPASS",
        enable_ecc => "FALSE",
        init_file => "initial_data.mif",
        intended_device_family => "Stratix V",
        lpm_type => "altsyncram",
        maximum_depth => 128,
        numwords_a => 128,
        numwords_b => 128,
        operation_mode => "DUAL_PORT",
        outdata_aclr_b => "NONE",
        outdata_reg_b => "UNREGISTERED",
        power_up_uninitialized => "FALSE",
        ram_block_type => "M20K",
        read_during_write_mode_mixed_ports => "DONT_CARE",
        widthad_a => 7,
        widthad_b => 7,
        width_a => 32,
        width_b => 32,
        width_byteena_a => 1
    )
    PORT MAP (
        address_a => wraddress,
        address_b => rdaddress,
        clock0 => clock,
        data_a => data,
        wren_a => wren,
        q_b => sub_wire0
    );
END SYN;

You could do that, but why not do it in your own file where you instantiate the ram and connect to it? It would make the code more readable.