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Altera_Forum
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9 years ago

Question about 1 port ram

Hello, I am new to VHDL. Currently I need to use M20K memory on Stratix V chip to store some data. I have two of these kind memory, m1 and m2. Each have 128 data, each data is 32 bit. I also use comp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

You could do that, but why not do it in your own file where you instantiate the ram and connect to it? It would make the code more readable.