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GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Questasim INTEl EDITION counter simulation

Hello. I'm using this vhdl code to make an 8 bit counter with enable. Quetasim Intel fpga does not increment the counter regularly (defined as variable). It goes from 'X' to '1' and then it...
Simulation
  • roeekalinsky's avatar
    roeekalinsky
    2 years ago

    @GOMEZ_IT, I think you were right, this looks like a simulator problem.

    I was able to reproduce your original observation, and it appears to be a bug in older versions of Questa, up to the version shipped with Quartus Pro 23.3.

    The version of Questa shipped with Quartus Pro 23.4 doesn't appear to exhibit this symptom. Or at least not with this test case. But I don't know if this was a known bug that got fixed, or if the symptom just went away with other changes in Questa. That's something you should confirm with Intel and/or Mentor/Siemens.

    For ease of testing, I modified your test case slightly to be able to run in a more minimalist command line mode, with console messages in lieu of waveforms. See attached zip.

    Running this test case with all the simulators I currently have available to me I got the following results:

    • Questa from Quartus Pro 22.2: bad
    • Questa from Quartus Pro 22.4: bad
    • Questa from Quartus Pro 23.1: bad
    • Questa from Quartus Pro 23.2: bad
    • Questa from Quartus Pro 23.3: bad
    • Questa from Quartus Pro 23.4: good
    • Modelsim DE 2022.4: good
    • ghdl 4.0.0-dev: good

    See attached log.txt for the above results.

    -Roee

roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
2 years ago

P.S. Questa bug notwithstanding, I would still advise you to avoid this sort of coding style where you're relying on language features that are more obscure, even if technically correct. It makes your code less readable. And you also increase your risk of treading into areas where even the tools may not be 100% conforming and may not be well tested, as we saw here.

And also, separately, that's sound advice from @sstrell about using a reset signal rather than relying on variable initialization. At least in RTL code that's intended for synthesis. Physical support for initial values varies between different FPGA device families and their various internal resource types. And synchronization issues... So there's plenty of opportunity to get yourself in trouble with that too if you're not careful.