New Contributor
Super ContributorHow is your .stp file set up? Is there anything unusual about it? I've never seen issues like this before with the .stp file flow.
Is the static assertions setting you mention an assignment you've created in the Assignment Editor?
New Contributorsstrell My stp. file is straight forward; it was created with the gui: Multiple signals, one trigger window, two triggers (AND and OR). However, what I did change was to add (and remove) a power-up trigger. However this was the first time, I used a power-up-trigger, but I don't think this is the root cause, because previously the same problems (with version 24.3) existed, and there was no power-up trigger
Yes, these settings enable Evaluation of the above mentioned assertion. If I deactivate them (never tried VHDL and SV individually) and cause the failure.
P.S. Please be aware, that I'm ooo from 13. Feb to 13 Mar, so please don't close this threat in the meanwhile!
