Forum Discussion
Try turning off the "Enable Signal Tap Logic Analyzer" checkbox from the settings and do a full compile (not just synthesis). Then turn it back on and do another full compile. If this was a brand new .stp file, your error doesn't make sense.
- MichaelL17 days ago
New Contributor
Sry. I was not precise in my post: I did a full compile (even removed generated files) including regenerating all IP files and not only the synthesis step. However, I will try turning off/on the checkbox.
- MichaelL16 days ago
New Contributor
sstrell Unfortunately, this had no effect.
Error(22148): VHDL error at sld_ela_control.vhd(1263): Failure: "The design file sld_ela_control.vhd is released with Quartus Prime software Version 25.3.0. It is not compatible with the parent entity. If you generated the parent entity using the Signal Tap megawizard, then you must update the parent entity using the megawizard in the current release."
Still what's very odd, that obviously this is only a (wrongfully triggered) assertion... When deactivating "static assertion support" everything "works" - however deactivating static assertion support is not what we want in our environment