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King22
New Contributor
New ContributorQuartusPro25.3 STA Error
I use QuartusPro25.3 , Device is AGILEX 7 , I found it often report error when in the "retiming " stage， Sometime I just modify my design to add some debug signal ， and it report error ，error massa...
King22New Contributor
New ContributorSorry ， I can't attach my design ，sometimes just change some debug signal and it report error ,
modify debug signal like below ( F-tile RX related signal )
wire [7:0] DBGO_FPGA_RX_06H = {
//rx_set_locktodata[1],edp_pll_lock[1],rx_is_lockedtodata_sys1,rx_is_lockedtoref_sys1, //4 bit use this error
rx_ready_sys1,rx_ready_sys0,rx_is_lockedtodata_sys1,rx_set_locktodata[0], //4 bit use this ok
rx_is_lockedtodata_sys0,rx_reset_ack_sys0,rx_reset_sys0,edp_reset_cdr[0]} ;
should I update QuatrusPro to 26.1
KennyT_altera
Super Contributor
Super Contributorclosing the thread since there are no further update.
