Quartus WE newbee - old logic designer

That's kind of an ugly one in a schematic(as far as I can tell). The bottom line is VHDL has some nice advantages, but so does schematic. For right now, it's probably worth learning a little VHDL and just dropping that into your schematic. For example, you can create a New VHDL file, go to Edit -> Insert Template -> Vhdl -> Constructs -> Sequential -> Case Statement. Follow the syntax and put into a VHDL architecture(you'll also need an Entity, which is basically a description of the top-level ports). Then modify the case to do your encoding. When you're done, go to File -> Create Symbol for Current File. Then add it into your schematic.

There is always verilog.

I'm not enjoying the process. I'm having real difficulty in just creating a simple design in Quartus. I can create a create a project , block design file/block symbol file no problem. But I'm having difficulty understanding the realization of that to the device. I'm missing something that is probably really simple and I sure haven't dug it out of Altera's documents.....:confused: Or found a rudametary simple Quartus 2 example.

Ok figured out my compile problems. So the next question would be where can I look for direction on the "connection" between a VHDL text file and a graphic bdf file?

Well, I've been making this much harder than it actually was....:) Got some VHDL working with graphic block design files and running some timing simulation. Thanks.