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Now the struggle is creating reasonable timing input files.
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You should use ModelSim and a VHDL test bench which is the best way to test your design.
If you are beginning with VHDL, you can get a training by Doulos. I had one a few year ago and it was really great. The instructor we had was a real expert and the training documents are very well made. In one week I learnt how to use VHDL. By yourself it will take ages and you will never be sure because many books and samples you find on the internet are full of bugs (for example about the sensitivity list).
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