New ContributorI am occuring a problem that i can't run the simulation of the wave, it always shows this error
C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vsim -c -do lab01.do
Error.
GPT says that it happens because it can't operate the .do document when ModelSim is working, but i have tried many ways including reinstall everything but it still doesn't work. i really need someone to help me, thanks.
Super ContributorHi OP,
Do you see any error messages? I don’t see any posted in your previous reply.
Please refer to the quick start guides below and run through the example design to get familiar with the simulation flow using Questa.
Questa Intel FPGA Edition Simulation Flow
Lite/Standard Edition:
https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html
Pro Edition:
https://www.intel.com/content/www/us/en/docs/programmable/691278/current.html
Regards,
Richard Tan
New ContributorDetermining the location of the ModelSim executable...
Using: C:\intelFPGA_lite\20.1\modelsim_ase\win32aloem
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off lab01 -c lab01 --vector_source="C:/DDDD/Waveform.vwf" --testbench_file="C:/DDDD/simulation/qsim/Waveform.vwf.vt"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sun Sep 28 14:16:02 2025
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off lab01 -c lab01 --vector_source=C:/DDDD/Waveform.vwf --testbench_file=C:/DDDD/simulation/qsim/Waveform.vwf.vt
Info (119006): Selected device 5CSEMA5F31C6 for design "lab01"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/DDDD/simulation/qsim/" lab01 -c lab01
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sun Sep 28 14:16:03 2025
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=C:/DDDD/simulation/qsim/ lab01 -c lab01
Info (119006): Selected device 5CSEMA5F31C6 for design "lab01"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file lab01.vo in folder "C:/DDDD/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4725 megabytes
Info: Processing ended: Sun Sep 28 14:16:03 2025
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
**** Generating the ModelSim .do script ****
C:/DDDD/simulation/qsim/lab01.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vsim -c -do lab01.do
Error.
This is all of the log file, same as you, I didn't see any error messages, so i really don't know what to do
Super ContributorI suspect something may have gone wrong during the software installation.
Please try uninstalling both Quartus and the simulator tool.
If possible, reinstall using the latest Quartus Prime version 24.1 along with the Questa – Altera FPGA Starter Edition, which requires a no-cost license.
After reinstalling, test using the example design provided in the user guide to see if the issue still persists.
Also, could you let me know which operating system you're currently using?
FYR:
5.3. Acquiring Free, No-Cost Licenses
Regards,
Richard Tan
Super ContributorPlease be informed that starting October 1st, the FPGA Forum on community.intel.com will be placed in read-only mode.
You will still be able to view and access existing content, but new posts, comments, or edits will no longer be permitted during this transition period.
For urgent technical support, we kindly ask that you reach out through Intel Premier Support (IPS) via your DFAE(Altera authorised distributors) engagement.
We appreciate your patience as we prepare for the official launch of the new FPGA forum on October 14th, where posting capabilities will resume.
Thank you for your continued support and understanding.
Regards,
Richard Tan
