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Avinash201040's avatar
Avinash201040
Icon for New Contributor rankNew Contributor
1 year ago

Quartus project file and setting file rename

hii,

i have a quartus project. i manually renamed the qpf and qsf file to some different name and according i updated the sdc constrains as well because some clock name got changed automatically while renaming the qsf and qpf.

now i am observing the fmax of a certain clock(dsp_clock) got reduced from 530 Mhz to 492 Mhz.

i could not find the exact issue.

what exactly can cause this much reduction in fmax.

am i following the correct procedure to rename the qsf and qpf or there is some other better way.

please let me know.

Hdl
Timing

1 Reply

  • HubertG's avatar
    HubertG
    Icon for Contributor rankContributor
    1 year ago

    We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

    Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.

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