Forum Discussion
11 Replies
- RichardT_altera
Super Contributor
Yes, there is a plan to fix this but it may takes time and I do not have the exact detail on when it will be fix. As this is subject to change.
- RichardT_altera
Super Contributor
Let me check this with the engineering team.
- RichardT_altera
Super Contributor
Fyi, the engineering team is working on this.
Please do expect that any work involves engineering may takes some time depending on the issue complexity.
Best Regards,
Richard Tan
- RichardT_altera
Super Contributor
May I know are these code for testbench usage?
- alexislms
Contributor
Not only, we mainly use it in our synthesizable code.
- RichardT_altera
Super Contributor
A workaround suggested by the engineering team is to change RTL a little bit.
By changing the assignment of unpacked type to bit by bit instead of complete.
for the given design example
module tb;
enum logic [7:0] {A, B, C} fsm [4];
logic [7:0] state [4];
assign state[0] = fsm[0];
assign state[1] = fsm[1];
assign state[2] = fsm[2];
assign state[3] = fsm[3];
//assign state = fsm;
endmodule
The engineering team will check with the tool vendor on fixing this issue.
- alexislms
Contributor
@RichardTanSY_Altera Thank you for the follow-up.
The workaround defeats the purpose of these data types, we will wait for the fix.
Regards,
- RichardT_altera
Super Contributor
Do you able to escape the error based on the last email that I sent?
- alexislms
Contributor
Can we expect this to be fixed in a new release?
- alexislms
Contributor
Thank you, please feel free to close the case.
- RichardT_altera
Super Contributor
With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.