Forum Discussion

alexislms's avatar
alexislms
Icon for Contributor rankContributor
3 years ago
Solved

Quartus Pro 22.2: enum logic vs logic : Error(16983): arrays have different elements

module tb; enum logic [7:0] {A, B, C} fsm [4]; logic [7:0] state [4]; assign state = fsm; endmodule Never had an issue with Vivado and never had an issue with Modelsim: https://www.edapl...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    Yes, there is a plan to fix this but it may takes time and I do not have the exact detail on when it will be fix. As this is subject to change.


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

A workaround suggested by the engineering team is to change RTL a little bit.

By changing the assignment of unpacked type to bit by bit instead of complete.


for the given design example


module tb;

enum logic [7:0] {A, B, C} fsm [4];

logic [7:0] state [4];

assign state[0] = fsm[0];

assign state[1] = fsm[1];

assign state[2] = fsm[2];

assign state[3] = fsm[3];

//assign state = fsm;

endmodule


The engineering team will check with the tool vendor on fixing this issue.