Quartus Prime Pro 21.3: Platform Designer Problem

Hi,

Some warnings showed up as well when i try to generate HDL of the sample file provided. Those warnings indicate that some ip files do not exist. Most likely these errors are caused by those missing ip files.

Make sure license is properly installed and not expired as well. And then try to recreate the design file.

Thanks.

Best regards,
Sheng

Hi Sheng,

Are you just getting warnings ? Or errors?

I tried removing and then re-adding all of the components and was able to get rid of the warnings about .ip files not found. These were apparently just stale .ip files being called out in the .qsf file.

However I am still getting the following errors:

Info: Done reading input file
Info: my_qsys: "Transforming system: my_qsys"
Warning: Translator MyComponent_0_avalon_slave_0_translator failed to match interface MyComponent_0.avalon_slave_0
Error: my_qsys: Connection (post-transform) is missing an end point: nios2_gen2_1.data_master->null
Error: my_qsys: Connection (post-transform) is missing an end point: clock_bridge_0.out_clk->null
Error: my_qsys: Connection (post-transform) is missing an end point: nios2_gen2_1.instruction_master->null
Error: my_qsys: Connection (post-transform) is missing a start point: null->MyComponent_0.avalon_slave_0
Error: my_qsys: Connection (post-transform) is missing a start point: null->onchip_memory2_1.s1
Error: my_qsys: Connection (post-transform) is missing a start point: null->nios2_gen2_1.debug_mem_slave
Error: Internal Error: Cannot generate a system with dangling connections.

I've found that if I only get the errors when the avalon slave in MyComponent is connected to the data_master out of the Nios II processor. If I export the avalon slave instead, it works fine. I think that the red-highlighted warning, which occurs just before the errors, may be the key to fixing this. But I don't understand what this warning means or how to fix it.

Thank you.

Terry

Hi Sheng,

I've tried doing this two different ways, but am getting the same error both ways.

First I tried the generic component (HDL mode) where I read in my VHDL file to create the generic component. Second, I tried the Component Editor where I also read in my VHDL file to create a component. Both of these methods result in the same error.

In both of these methods, Platform designer reads in and analyzes the VHDL file, and puts a copy of it down in the ip folder that it creates. So it should know about the VHDL file and where to find it.

The problem seems to be on the other end with the Avalon Slave Translator component not being found. In previous versions of Qsys, there was an actual component called "Avalon-MM Slave Translator" that could be used for this sort of thing, instead of using a custom VHDL file. With v21.3 Platform Designer, that component does not show up in the list of available components. I can see this component in the Quartus Pro install package in the ip/altera/merlin/altera_merlin_slave_translator folder, but it's not available in the list of components in Platform Designer.

I've tried several different IP search paths in Platform Designer, but all result in the same error message.

Thanks,

Terry

The translator is used as part of the interconnect generated by PD, not something you usually have to add to a system design yourself. Can you post your code, at least the top-level ports and your _hw.tcl file?

Sheng,

I replaced the oe_n signal with a read signal and it now seems to be working OK. Do you know if that is something that will be fixed in an upcoming version of Quartus Prime Pro?

Thank you!

--

Terry