Forum Discussion
Quartus Prime Pro 21.3: Platform Designer Problem
- 4 years ago
I try to recreate the example design attached in platform designer.
I found out that if outputenable port under avalon_slave_0 is removed the errors disappear and HDL can be generated. The errors come out if outputenable port is added.
Hi Sheng,
Are you just getting warnings ? Or errors?
I tried removing and then re-adding all of the components and was able to get rid of the warnings about .ip files not found. These were apparently just stale .ip files being called out in the .qsf file.
However I am still getting the following errors:
Info: Done reading input file
Info: my_qsys: "Transforming system: my_qsys"
Warning: Translator MyComponent_0_avalon_slave_0_translator failed to match interface MyComponent_0.avalon_slave_0
Error: my_qsys: Connection (post-transform) is missing an end point: nios2_gen2_1.data_master->null
Error: my_qsys: Connection (post-transform) is missing an end point: clock_bridge_0.out_clk->null
Error: my_qsys: Connection (post-transform) is missing an end point: nios2_gen2_1.instruction_master->null
Error: my_qsys: Connection (post-transform) is missing a start point: null->MyComponent_0.avalon_slave_0
Error: my_qsys: Connection (post-transform) is missing a start point: null->onchip_memory2_1.s1
Error: my_qsys: Connection (post-transform) is missing a start point: null->nios2_gen2_1.debug_mem_slave
Error: Internal Error: Cannot generate a system with dangling connections.
I've found that if I only get the errors when the avalon slave in MyComponent is connected to the data_master out of the Nios II processor. If I export the avalon slave instead, it works fine. I think that the red-highlighted warning, which occurs just before the errors, may be the key to fixing this. But I don't understand what this warning means or how to fix it.
Thank you.
Terry
- ShengN_altera4 years ago
Super Contributor
Hi Terry,
Same thing here. When I try to export the avalon slave, everything works fine.
Then I go to generic_component_0/Component Instantiation/HDL/Files and analyze HDL file MyComponent.vhd. After analyzing, i get error states that module not found. Most probably this is the main cause for the errors.
Make sure MyComponent.vhd file exists and working as well as its directory is correct.
Thanks.
Best regards,
Sheng