Forum Discussion
Occasional ContributorQuartus Prime Pro 21.3: Platform Designer Problem
I try to recreate the example design attached in platform designer.
I found out that if outputenable port under avalon_slave_0 is removed the errors disappear and HDL can be generated. The errors come out if outputenable port is added.
Super ContributorThe translator is used as part of the interconnect generated by PD, not something you usually have to add to a system design yourself. Can you post your code, at least the top-level ports and your _hw.tcl file?
GLT1Sure,
The attached qar is slightly different than the original one I posted. This version uses the component editor instead of the generic component (HDL) method. Both methods result in the same error message.
The Qsys file is in the src folder (my_qsys.qsys). Just open that in the Platform Designer and click "Generate" to reproduce the error.
Thanks,
Terry
- ShengN_altera
I try to recreate the example design attached in platform designer.
I found out that if outputenable port under avalon_slave_0 is removed the errors disappear and HDL can be generated. The errors come out if outputenable port is added.
- GLT1
Sheng,
I'll give that a try today and let you know how it goes.
Thanks,
Terry
