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Siyeon's avatar
Siyeon
Icon for New Contributor rankNew Contributor
3 years ago

Quartus prime lite edition 20.1.1 gate level simulation

I want to perform gate level simulation in Quartus Prime Lite Edition. After selecting "Tools → Run simulation tool → gate level simulation" and viewing the ModelSim waveforms, I noticed that the da...
Hdl
Simulation
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Check this link https://www.intel.com/content/www/us/en/docs/programmable/683080/22-1/simulation-levels.html

Note: Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is supported only for the Arria® II GX/GZ, Cyclone® IV, MAX® II, MAX® V, and Stratix® IV device families.. Use Timing Analyzer static timing analysis rather than gate-level timing simulation.


Thanks,

Best Regards,

Sheng