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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus Illegal configuration of I/O primitive inst: port ERROR

All,

Schematic entry:

I am not seeing what I am doing wrong here.

I have a primitive ALT_IOBUF tied to a primitive BIDIR pin.

The control input is tied to 1 pin (master)

The OUTPUT is tied to 1 and only 1 BIDIR pin (nc5)

The OUT Going buffer is tied to 1 net (nc[5])

The IN Coming buffer is tied to 1 net (ncin[5])

Then I get the error.

What am I doing wrong.

Quartus 9.0 (yeah I know there are newer free versions, but this has been working for me)

Windows10: so far all my other designs have not had any issues

(see attachment)

Keith

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi,

    I assume this is just part of your design, and that master, nc[5], and ncin[5] are connected somewhere.

    I tried to duplicate your schematic in quartus 13.0, and I get this error:

    Error (17037): Illegal configuration of I/O primitive inst: port "io" should be directly connected to a single bidir pin.

    But, I also get this warning:

    Warning (275080): Converted elements in bus name "nc" using legacy naming rules. Make any assignments on the new names, not on the original names.

    Warning (275081): Converted element name(s) from "nc[5]" to "nc5"

    I think Quartus renames any bus net name such as bus[x] to busx. So you end up with both the input and i/o pin on ALT_IOBUF connected to net nc5.

    I tried renaming the net nc[5] to ncout[5], and then the error went away for me.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thanks for the info. I WAS able to get that module to work.... but..... now when I use that module in the rest of my design, I get the same error again....

    I did the work around and now "master" controls MUXs for producing the clk waveforms or "not master" using waveforms derived from another IC.

    I have also ran into the problem using net naming issues. Such as the nc5 and nc4 are nets in a bus nc[5..0], but I was informed that the the individual net names have to be established as nc[5] and nc[4].

    So I just label them to where I don't get an error or warning. (one project I use labeling as nc[X] and the other I use labeling as ncX

    I think I am making it work.

    Thanks again,

    Keith