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Altera_Forum
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9 years ago

Quartus Illegal configuration of I/O primitive inst: port ERROR

All, Schematic entry: I am not seeing what I am doing wrong here. I have a primitive ALT_IOBUF tied to a primitive BIDIR pin. The control input is tied to 1 pin (master) The OU...
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Altera_Forum
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9 years ago

Thanks for the info. I WAS able to get that module to work.... but..... now when I use that module in the rest of my design, I get the same error again....

I did the work around and now "master" controls MUXs for producing the clk waveforms or "not master" using waveforms derived from another IC.

I have also ran into the problem using net naming issues. Such as the nc5 and nc4 are nets in a bus nc[5..0], but I was informed that the the individual net names have to be established as nc[5] and nc[4].

So I just label them to where I don't get an error or warning. (one project I use labeling as nc[X] and the other I use labeling as ncX

I think I am making it work.

Thanks again,

Keith