Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design

@BoonBengT_Altera ,

Thanks for getting back to me. Sorry for slow reply.

I'm not sure what you mean by 'trigger', the Verilog generate-for loop instantiates parallel instances of the IP core. If the for loop is large, then during compilation the memory usage is untenable.

SOMEBIGNUMBER is approximately 200. I cannot share the exact HLS code, but it is essentially a cumulative sum across 128 inputs. Here is some psuedo code:

float myHlsCore(16bit integer stream_in)

{

static float runSum = 0;

for c=1:128

runSum+= stream_in[c];

return runSum;

}

We have partially solved the issue by creating a very large swap file on the system (~500GB), but this is not a realistic solution as memory access is extremely slow on the swap.

Now the compilation process fails, saying the design cannot be routed, despite resource usage being less than 60%. It is a slightly different issue, but I think they are related, and I do not think that the swap file is a good solution to the original problem either.

Thanks,

Chris