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Re: Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design
@BoonBengT_Altera , Thanks for getting back to me. Sorry for slow reply. I'm not sure what you mean by 'trigger', the Verilog generate-for loop instantiates parallel instances of the IP core. If the for loop is large, then during compilation the memory usage is untenable. SOMEBIGNUMBER is approximately 200. I cannot share the exact HLS code, but it is essentially a cumulative sum across 128 inputs. Here is some psuedo code: float myHlsCore(16bit integer stream_in) { static float runSum = 0; for c=1:128 runSum+= stream_in[c]; return runSum; } We have partially solved the issue by creating a very large swap file on the system (~500GB), but this is not a realistic solution as memory access is extremely slow on the swap. Now the compilation process fails, saying the design cannot be routed, despite resource usage being less than 60%. It is a slightly different issue, but I think they are related, and I do not think that the swap file is a good solution to the original problem either. Thanks, Chris2.2KViews0likes0CommentsQuartus II Synthesis - System Memory Issues for Large Stratix 10 Design
Hello, I have a Stratix 10 design that is based around an ip core generated using Intel's HLS. The core does some simple floating point operations and by itself uses very few resources (1 DSP, a few hundred flops etc). This core sits inside a generate statement like this: generate for(i = 0; i < SOMEBIGNUMBER; i=i+1) myhlscore u0 (inputs, outputs); ... The design works and is proven in simulation and in hardware. The problem comes when I try to increase the value of SOMEBIGNUMBER. Despite there being adequate resources, using values above 200 or so make the synthesis tool run out of memory. I cannot alleviate this easily by adding more memory - I already tried synthesizing on a computer with 256GB memory and a 200GB swap space and quartus ate it all up before dying. I'm using a .ip file from HLS right now. I'm wondering is there is some way to pre-synthesis the module and keep the results, or is there someway I need to write the generate statement so that it caches less? Perhaps there are some synthesis settings I can change? We tried using a design partition, but the elaboration stage still exceeds the 120 GB of memory. Thanks, C2.4KViews0likes8Comments