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CADAMS's avatar
CADAMS
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4 years ago

Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design

Hello, I have a Stratix 10 design that is based around an ip core generated using Intel's HLS. The core does some simple floating point operations and by itself uses very few resources (1 DSP, a f...
BoonBengT_Altera's avatar
BoonBengT_Altera
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4 years ago

Hi @CADAMS,

Thank you for posting in Intel community forum and hope all is well.
If I understand correctly the situation I would say the looping might be the cause here.

Hence would recommend to look into pipelining the loops which will enable parallelism.
Here are some explanation on the concept, and would recommend to look into the guide of writing the loop in HLS.
Hope that clarify.

Best Wishes
BB

CADAMS's avatar
CADAMS
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4 years ago

No that's not the issue. The loop in my original post is a generate statement (RTL) wrapping the HLS core. I don't think the guides you sent are relevant.

Cheers,

C