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Altera_Forum's avatar
Altera_Forum
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15 years ago

Quartus EDA Netlist Writer

Hi,

Using Altera Model-Sim to do a gate level simulation. The .vo file that is produced doesn't seem to be modeling the internal RAM's correctly. In the design they are instantiated as 12bit but the EDA netlist has them as 4 bits.

Any help on this?

Regards,

Rob

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    So far, you're not reporting an error, I think. Internal RAM doesn't offer a 12 Bit mode, depending on the memory size, it may be possibly split into 3x4 bit. If you observe functional errors, you should describe them in detail.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I wasn't getting an error. I just noticed that the ram was 4 bits wide. But as you mention, it did instantiate it as three 4-bit memories.

    Thank you,

    Rob