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Altera_Forum
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15 years ago

Quartus EDA Netlist Writer

Hi, Using Altera Model-Sim to do a gate level simulation. The .vo file that is produced doesn't seem to be modeling the internal RAM's correctly. In the design they are instantiated as 12bit...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I wasn't getting an error. I just noticed that the ram was 4 bits wide. But as you mention, it did instantiate it as three 4-bit memories.

Thank you,

Rob