Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Quartus Designs away state machines

I am a professor that has assigned a stop watch project to my class that displays on an LCD. The students are implemting the project in VHDL primarily using state machine constructions. Although I can find nothing wrong with their VHDL code, Quartus consistently designs away a number of the states, all of which are critical for setting up and operating the LCD. Does anyone have any guidance in how to convince Quartus to leave the state machines alone. I've tried encoding the machine using one-hot and I've tried enablign the "what you see is what you get" option to prevent the change but to no avail.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I compiled your example with Quartus V9.0 with default synthesis settings, and according to the State Machine Viewer tool, both FSM with 6 states each have been recognized. Thus I wonder what happened different in your test. I didn't further check the design's functional behaviour.

    Regards,

    Frank
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Thanks for the response. The state viewer will show all states but when you simulate it or actually download it into a development board a number of the states are missing.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    If they are shown in the State Machine Viewer, they have not been designed away. In case of doubt, you can verify the existence of state variables also in the Technlogy Map Viewer, that is displaying the gate level design.

    It may be the case, that you don't see the states in simulation because they are skipped due to inappropriate switching conditions. As I said, I didn't check the functional behaviour. But then, your error report is rather inaccurate. To avoid further misunderstandings, you should also provide your simulation waveform.

    P.S.: I see, that part of the design, e. g. the clock dividers is probably not operating as intended. As a result, state2 FSM is stuck in initial state.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I can see that some counters are undefined when they reach their maximum value.For example, in the below process, clkcount is not defined when it reaches count 2

    --- Quote Start ---

    process(clk)

    begin

    if(clk'event and clk ='1') then

    if(clkcount = 2) then --reset to 28

    state2clk <= '1';

    else

    clkcount <= clkcount + 1;

    state2clk <= '0';

    end if;

    end if;

    end process;

    --- Quote End ---

    similarly in the following process, state2clkcount is not defined at count 6

    --- Quote Start ---

    process(state2clk)

    begin

    if(state2clk'event and state2clk ='1') then

    if(state2clkcount = 6) then

    onesclk <= '1';

    else

    state2clkcount <= state2clkcount + 1;

    onesclk <= '0';

    end if;

    end if;

    end process;

    --- Quote End ---

    Moreover, the design is using multiple clks(can be unsafe from fpga perspective as opposed to ASIC). You should keep number of clks to a minimum and possibly one system clk will do by using enable signal to control rates.

    You can also neatly divide all your clks in one process instead of a mixture of processes and lpm counter instantiations:

    The following single process cascades as many counters as you want, count1 is enabled always, count2 is enabled only when count1 reaches maximum

    and so on. They are clked by one system clk.

    --- Quote Start ---

    -- cascade as many counters as you want

    process(clk)

    begin

    if(clk'event and clk ='1') then

    .....if(count1 /= 2) then

    ..........count1 <= count1 + 1;

    ......else

    ..........count1 <= 0;

    ..........if(count2 /= 6)then

    ...............count2 <= count2 + 1;

    ..........else

    ...............count2 <= 0;

    ...............if(count3 /= 11)then

    ....................count3 <= count3 + 1;

    ...............else

    ....................count3 <= 0;

    ....................if(count4 /= 63)then

    .........................count4 <= count4 + 1;

    ....................else

    .........................count4 <= 0;

    .........................if(count5 .....etc)

    .............................etc

    .........................end if;

    ....................end if;

    ................end if;

    ............end if;

    ......end if;

    end if;

    end process;

    --- Quote End ---

    Finally, don't forget to add reset to all counting.