Quartus Designs away state machines

If they are shown in the State Machine Viewer, they have not been designed away. In case of doubt, you can verify the existence of state variables also in the Technlogy Map Viewer, that is displaying the gate level design.

It may be the case, that you don't see the states in simulation because they are skipped due to inappropriate switching conditions. As I said, I didn't check the functional behaviour. But then, your error report is rather inaccurate. To avoid further misunderstandings, you should also provide your simulation waveform.

P.S.: I see, that part of the design, e. g. the clock dividers is probably not operating as intended. As a result, state2 FSM is stuck in initial state.