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Altera_Forum
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16 years ago

Quartus Designs away state machines

I am a professor that has assigned a stop watch project to my class that displays on an LCD. The students are implemting the project in VHDL primarily using state machine constructions. Although I ca...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I compiled your example with Quartus V9.0 with default synthesis settings, and according to the State Machine Viewer tool, both FSM with 6 states each have been recognized. Thus I wonder what happened different in your test. I didn't further check the design's functional behaviour.

Regards,

Frank