Quartus Compiles MAX10 Project Without Errors But ADC Block Not Used (0/1 in Flow Summary)

Hi,

I'm working on a project with a MAX10 FPGA (10M08SAE144C8G) in Quartus Prime 24.1, using the Modular ADC IP core. My design synthesizes and compiles with no errors or warnings. However, in the Flow Summary after compilation, the "ADC blocks" line still says 0 / 1 (0%), which means the ADC is not actually implemented.

No errors or warnings during synthesis or implementation.

ADC is connected in the Platform Designer (QSYS) system and in my top-level design.

All other resources are counted and mapped, except the ADC.

I can see the ADC signals in my design, but the block is not present in the final bitstream.

Why would Quartus synthesize and compile my project without using the ADC block, even though it's instantiated and connected?.

Are there any special settings or steps to ensure the Modular ADC is included in the design?

Thanks for any suggestions!