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Ranjith21's avatar
Ranjith21
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Quartus 23.4 shows 0.0 BER but negative eye height values

Hi,

I am running BER test for 2 FPGAs. I am transmitting from Tx pin of first FPGA and receiving on Rx pin on second FPGA. Using Quartus 23.4 here.

Both are Agilex F-tile F-series FPGAs. There is a total trace length of 13 inches between the FPGAs and the speed is 28Gbps NRZ PRBS31.

I set up a autosweep to sweep through different tap values in order to tune the channel

I notice that the results show negative eye height for many iterations but the corresponding BER is zero (see attached pdf)

How can this be possible?

Negative eye height means that the eye is closed. In this case we should expect maximum BER

Please help me understand what is going on here

Thanks,

Ranjith

Platform

13 Replies

  • Ranjith21's avatar
    Ranjith21
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Adding more details:

    The insertion loss between the FPGAs is ~15db.

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Ranjith21,


    May I know the OPN board number that you use?


    Best regards,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Ranjith21,


    Negative eye height value means that the measurement height is calculated by Eye Center-to-top (Middle) minus Eye Center-to-bottom(Middle). For the positive height value, the measurement height is calculated from eye center to the top of the eye.


    Best regards,

    zying



  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Ranjith21,


    BER issue always related to channel loss. Please do make sure the RX channel is receiving data before starting eye measurement.


    Best regards,

    zying


  • Ranjith21's avatar
    Ranjith21
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello @ZiYing_Intel

    This is the FPGA part number AGFB027R31C2E2V

    I have ensured that the RX channel is receiving data before starting eye measurement

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Ranjith,


    Could you try to adjust the main tap value?


    Best regards,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Ranjith,


    Please do let me know if there is any update on the BER value when you adjust the main tap value.


    Best regards,

    zying


    • Ranjith21's avatar
      Ranjith21
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi @ZiYing_Intel

      I am sweeping different values for main tap as shown in the attached PDF. Still negative eye height with zero BER exists, please refer .pdf attached

      Thanks,

      Ranjith

      • Ranjith21's avatar
        Ranjith21
        Icon for Occasional Contributor rankOccasional Contributor
        2 years ago

        @ZiYing_Intel

        Here is another autosweep showing the same issue

        Attached

        Thanks,

        Ranjith

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Ranjith,

    Could you try to increase the amplitude? Because I assume that the receiver side still have the minimum height limit on there.

    From the analog side, the transmitter usually larger a bit than the receiver. The receiver side will have the minimum height limit on there and if the height is smaller than the minimum requirement, the signal might occur a lot error (BER).

    Best regards,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Best regards,

    zying


    • Ranjith21's avatar
      Ranjith21
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      @ZiYing_Intel

      Please check my comments. I have updated my responses on 02-20-2024

      Please scroll up

      Thanks,

      Ranjith

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Ranjith,


    I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Best regards,

    zying