Forum Discussion
SyafieqS
Super Contributor
2 years agoHi Julia,
Update:
The issue appears to occur when is_pa_core (is phase aligned to core) is set to "true", which enables feedback compensation via iqtxrxclk wires. However, this mode doesn't have a valid feedback timing model, so is_pa_core can only be set to "false". A possible workaround would be to disable is_pa_core and the iqtxrxclk parameters. Try editing phyfpll/synth/phyfpll.v and change these 3 parameters:
is_pa_core from "true" to "false"
cmu_fpll_pll_iqclk_mux_sel from "iqtxrxclk0" to "power_down"
cmu_fpll_fpll_iqtxrxclk_out_enable from "fpll_iqtxrxclk_out_enable" to "fpll_iqtxrxclk_out_disable"
I am able to pass the flow with the workaround. Please validate this at your end and let me know any update.
The fix will be planned soon.