NiSyl
New Contributor
1 year agoQuartus 22.3 Pro - Implementation Fails at Analysis & Synthesis Without Errors
Hello,
I'm experiencing an issue with Quartus 22.3 Pro while working on an FPGA design for an Altera device. The Analysis & Synthesis stage fails without displaying any specific errors or warnings in the Messages window. Here are the details of my setup:
- Quartus Version: 22.3 Pro
- Target FPGA Device: Aria 10, 10AX115H2F34I2LG
- Scripting/GUI: GUI
- Operating System: Linux
What I Have Tried So Far:
- Checked for missing files – All source files (.v, .sv, .vhd) are present and listed in the project.
- Reviewed warnings/messages – No specific errors or warnings appear, only a failed Analysis & Synthesis.
- Performed a clean build – Deleted db/ and incremental_db/, then recompiled with quartus_sh --clean.
- Checked licensing – Used quartus_sh --t check_license.tcl, and there were no reported issues.
- Verified IP cores – All cores were regenerated using quartus_ipgenerate --recreate_all.
Request for Help:
- What other debugging steps can I try to identify the root cause?
- Are there any known issues with Quartus 22.3 Pro that might cause this behavior?
- Any logs or specific reports I should check?
Any help would be greatly appreciated!
Thanks in advance.