Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Quartus 10.0 complains of nested clock gating scheme

Hi,

I replace the asic clock gating cell with ALTCLKCTRL module when I run quartus 10.0 to build SOF file. However, the process stops because the input clock of ALTCLKCTRL module is another ALTCLKCTRL module's output clock.

What can I do to solve this problem?

Is that a limitation of Altera tools?

BTW, in order to skip that error, I use RTL coding style of clok gating function as below:

module fpga_ckgate (

input ena,

input inclk,

output outclk

);

reg clk_enable_lat;

always @ (inclk or ena) begin

if (~inclk)

clk_enable_lat = ena;

end

assign outclk = inclk & clk_enable_lat;

endmodule

is there anything wrong?

I got a lot of critical messages from Design Assistant and it says -

C101 Gated Clock Should be Implemented According to Altera Standard Scheme

If ALTCLKCTRL doesn't support nested clock gating scheme, please tell me how to modify the RTL code to get rid of those critical messages.

Thanks ahead for the reply.

Best Regrads,

Acme

12 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    c) Of course. You need to constrain all clocks in your design, either external or internally generated.

    Also, you may have to set I/O constrains for the DRAM interface.

    a) create_clock is for externally provided clocks; for internally generated clocks (by PLLs or logic), you should use the create_generated_clock command instead.

    However, for PLL generated clocks, just use the derive_pll_clocks command instead which does it all for you.

    b) One you set constraints for the PLL clocks, they'll show up in the reports.

    PS: The reason I asked about -add is that -add is meant when you need to set more than one clock constrain to the same target. I'm not sure what happens if you use -add in the very first clock constrain you set to a given target.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Rbugalho,

    After a lot of trials, our SW confirmed that the SOF file which is built based on Synplify flow works well.

    Now, I am trying to use the VQM file(represent CPU) generated by Synplify to build whole chip SOF with Quartus 10.0.

    My question here is how to configure Quartus not to touch any function in the VQM file?

    As I understand, Quartus tool will be used for P&R(place and rout) even in the pure Synplify flow. Please correct me if I am not right.

    So, if pure synplify flow works, there is no reason Quartus+VQM will fail unless some options in the Quartus lead to some modifications in the design of VQM during fitting/P&R ...

    If need, I can show you global setting in my QSF file.

    thanks,

    acme