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Altera_Forum
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14 years ago

Quartus 10.0 complains of nested clock gating scheme

Hi, I replace the asic clock gating cell with ALTCLKCTRL module when I run quartus 10.0 to build SOF file. However, the process stops because the input clock of ALTCLKCTRL module is another ALT...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi Rbugalho,

After a lot of trials, our SW confirmed that the SOF file which is built based on Synplify flow works well.

Now, I am trying to use the VQM file(represent CPU) generated by Synplify to build whole chip SOF with Quartus 10.0.

My question here is how to configure Quartus not to touch any function in the VQM file?

As I understand, Quartus tool will be used for P&R(place and rout) even in the pure Synplify flow. Please correct me if I am not right.

So, if pure synplify flow works, there is no reason Quartus+VQM will fail unless some options in the Quartus lead to some modifications in the design of VQM during fitting/P&R ...

If need, I can show you global setting in my QSF file.

thanks,

acme