Quartus 10.0 complains of nested clock gating scheme

c) Of course. You need to constrain all clocks in your design, either external or internally generated.

Also, you may have to set I/O constrains for the DRAM interface.

a) create_clock is for externally provided clocks; for internally generated clocks (by PLLs or logic), you should use the create_generated_clock command instead.

However, for PLL generated clocks, just use the derive_pll_clocks command instead which does it all for you.

b) One you set constraints for the PLL clocks, they'll show up in the reports.

PS: The reason I asked about -add is that -add is meant when you need to set more than one clock constrain to the same target. I'm not sure what happens if you use -add in the very first clock constrain you set to a given target.