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Altera_Forum's avatar
Altera_Forum
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9 years ago

qsys sdram controller address mapping

Hi,

In a qsys design I'm using the SDRAM Controller Core to control either a 2Mx32 or 4Mx32 SDRAM. My goal is to use a common FPGA image rather than have an image that is unique for each size of SDRAM. Thus I have specified the larger 4Mx32 device in my design. Operationally both devices work, but the resulting address map for the 2Mx32 is problematic. Rather than having one 8MB chunk at address 0 and a mirror at address 0x800000, the map is 4MB chunk 0, mirror of chunk 0, 4MB chunk 1, mirror of chunk 1. This is due to the way the SDRAM controller maps the avalon address signals to the SDRAM address pins. For my use case of a 4Mx32 (AS4C4M32S), the controller maps the address signals as follows:

A9-A2 -> column 7-0

A10 -> bank address 0

A22-A11 -> row 11-0

A23 -> bank address 1

Note how A23 is connected to bank address 1. This is what is causing the fragmented mirroring.

Since row address 11 does not exist on the 2Mx32 device, I need to have A23 map to row address 11. This would give me an 8MB contiguous chunk starting at 0, followed by an 8MB mirror when using a 2Mx32 device. Is there an easy way to achieve this? I'd prefer not to have to hack the SDRAM controller, if that's even possible.

thanks,

galen

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    I don't think there is an easy way to get what you want. You can hack the SDRAM controller, or create your own IP (an address translating bridge) in front of the SDRAM within your Qsys system.

    Having already hacked the SDRAM controller, I can say it is not that bad. It is generated in clear text and once you wrap your head around what it's doing and their labelling scheme it's not difficult to navigate around. Skim the file and search for "f_bank" and "active_bank" and you'll quickly see where the bank assignments are picked out of the Avalon-MM side address bits. An annoyance here is your edits get overwritten each time you generate the system.

    If you're going this route, I would recommend creating a dummy Qsys system with just the SDRAM and the "Avalon-MM Traffic Generator and BIST Engine" component to get some confidence in your modifications.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Thanks for the response, and for confirming what I suspected. If I decide to try to fix the address map, I suspect I will try to create a bridge. It seems like this could be a very simple shim between slave and master. Hopefully it wouldn't even need any registers, just a passive rewiring of the address bus.