qsys sdram controller address mapping

I don't think there is an easy way to get what you want. You can hack the SDRAM controller, or create your own IP (an address translating bridge) in front of the SDRAM within your Qsys system.

Having already hacked the SDRAM controller, I can say it is not that bad. It is generated in clear text and once you wrap your head around what it's doing and their labelling scheme it's not difficult to navigate around. Skim the file and search for "f_bank" and "active_bank" and you'll quickly see where the bank assignments are picked out of the Avalon-MM side address bits. An annoyance here is your edits get overwritten each time you generate the system.

If you're going this route, I would recommend creating a dummy Qsys system with just the SDRAM and the "Avalon-MM Traffic Generator and BIST Engine" component to get some confidence in your modifications.