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Altera_Forum's avatar
Altera_Forum
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9 years ago

qsys sdram controller address mapping

Hi, In a qsys design I'm using the SDRAM Controller Core to control either a 2Mx32 or 4Mx32 SDRAM. My goal is to use a common FPGA image rather than have an image that is unique for each size ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks for the response, and for confirming what I suspected. If I decide to try to fix the address map, I suspect I will try to create a bridge. It seems like this could be a very simple shim between slave and master. Hopefully it wouldn't even need any registers, just a passive rewiring of the address bus.