Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Qsys mm_interconnect - how to control size

I've got a largeish QSYS system with HPS and VIP suite modules, some dual-port RAM, etc. I've got a JTAG-MM Master hooked up to the control ports of the VIP modules, and I've got the HPS LW_AXI hooked up to those same control ports and some of the dual-port RAM. When my QSYS system is built, I get 5 mm_interconnect modules, and 4 of them are some 300-600 ALMs and the 5th is nearly 4000 ALMs. I've got them all clocked with the same clock, but for some reason this interconnect needs to take up a large percentage of my chip which I can ill afford. Would it be better to use the full AXI bus, not the lightweight one?

Cheers,

Simon

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Qsys generates logic for every interconnection, and if you connect dissimilar masters to the same slave, the logic at each connection point can explode.

    Try inserting a pipeline bridge such that all your slaves have only the pipeline bridge as a master, and then connect your masters to the pipeline bridge.

    I believe this is detailed in an appnote describing how to optimize Qsys designs, but I can't find the reference at the moment.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    I believe this is detailed in an appnote describing how to optimize Qsys designs, but I can't find the reference at the moment.

    --- Quote End ---

    Do you have this app note somewhere available?