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Altera_Forum's avatar
Altera_Forum
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10 years ago

Qsys mm_interconnect - how to control size

I've got a largeish QSYS system with HPS and VIP suite modules, some dual-port RAM, etc. I've got a JTAG-MM Master hooked up to the control ports of the VIP modules, and I've got the HPS LW_AXI hook...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Qsys generates logic for every interconnection, and if you connect dissimilar masters to the same slave, the logic at each connection point can explode.

Try inserting a pipeline bridge such that all your slaves have only the pipeline bridge as a master, and then connect your masters to the pipeline bridge.

I believe this is detailed in an appnote describing how to optimize Qsys designs, but I can't find the reference at the moment.