Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

[Qsys] LPDDR2 Controller (UniPHY): HDL generation fails.

From the TerasIC Cyclone V GX Starter Kit (C5G) system cd v.1.2.2. (http://www.terasic.com/downloads/cd-rom/c5g/c5g_v.1.2.2_systemcd.zip), I use Qsys (16.1 under Windows 10 64-bits) to re-generate the HDL from

[...]\C5G_v.1.2.2_SystemCD\Demonstrations\C5G_LPDDR2_Nios_Test\C5G_QSYS.qsys.

Unfortunately, I receive the following error: 

Error: s0: Error during execution of "{C:/intelfpga_lite/16.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{C:/intelfpga_lite/16.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: s0: ]2;Altera Nios II EDS 16.1 C:/intelfpga_lite/16.1/quartus/bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../C5G_QSYS_mem_if_lpddr2_emif_s0_AC_ROM.hex -inst_rom ../C5G_QSYS_mem_if_lpddr2_emif_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_MR1_CALIB=01100011000000010000 -DAC_ROM_MR1=01100011000000010000 -DAC_ROM_MR2=00000101000000100000 -DAC_ROM_MR3=00000010000000110000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DNON_DES_CAL=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=10 -DHARD_PHY=1
Error: s0: UniPHY Sequencer Microcode Compiler
Error: s0: Copyright (C) 2016  Intel Corporation. All rights reserved.
Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: s0: Info: Writing ../C5G_QSYS_mem_if_lpddr2_emif_s0_AC_ROM.hex ...
Error: s0: Info: Writing ../C5G_QSYS_mem_if_lpddr2_emif_s0_inst_ROM.hex ...
Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing ../sequencer_auto_h.sv ...
Error: s0: Info: Microcode compilation successful
Error: s0: C:/intelfpga_lite/16.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: s0: Error: 0x80070057
Error: s0: 
Error: s0: 
Error: s0: 
Error: s0: child process exited abnormally
Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred
    while executing
"error "An error occurred""
    (procedure "_error" line 8)
    invoked from within
"_error "Cannot find $seq_file""
    ("if" then script line 2)
    invoked from within
"if { == 0} {
		_error "Cannot find $seq_file"
	}"
    (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
    invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage ]"
    ("if" then script line 2)
    invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
		set calc_mem_size  > 0} {
		set seq_mem_size "
    (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
    invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "LPDDR2" $tmpdir QUARTUS_SYNTH"
    invoked from within
"foreach generated_file  {
		set file_name [file tail $gene..."
    (procedure "generate_synth" line 8)
    invoked from within
"generate_synth C5G_QSYS_mem_if_lpddr2_emif_s0"

I suspect the error to originate from the scripts called to generate the lpddr2 sdram controller with uniphy IP component but have too limited knowledge to track down the error.

I also found the solution to a somewhat similar error message (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd02192013_986.html) but this didn't solve the issue (or I did it wrong).

Finally, I don't believe the error could come from the project as I didn't modify it and it seems to have been generated correctly by TerasIC engineers under 13.1.

Thanks.

10 Replies

  • jackhab's avatar
    jackhab
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    I had this problem with Quartus 15.1.2.

    Solved it by uninstalling Windows Subsystem for Linux (WSL).

    • ORoch's avatar
      ORoch
      Icon for New Contributor rankNew Contributor
      6 years ago

      Thank you!

      I also had a similar issue on WIndows 10, and solved it by uninstalling WSL, although maybe there is a less drastic solution.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    So you're getting this error when you try to generate the system in Qsys? It looks like you're using the Lite version of Quartus Prime which does not include a license to the IP Base Suite which includes the memory controller IP (https://www.altera.com/products/intellectual-property/design/ip-base-suite.html). Not sure if that's the issue.

    Try this: in Qsys, double-click the controller to open its parameter editor. Edit a setting and then put it back to its original value. Then try generating the system again.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    So you're getting this error when you try to generate the system in Qsys?

    --- Quote End ---

    Yes.

    --- Quote Start ---

    It looks like you're using the Lite version of Quartus Prime which does not include a license to the IP Base Suite which includes the memory controller IP (https://www.altera.com/products/intellectual-property/design/ip-base-suite.html).

    --- Quote End ---

    Indeed, I am. If this is the reason, shouldn't I receive a clearer error message? (e.g. when using the sdram controller, I receive the message "sdram controller will only be supported in quartus prime standard edition in the future release"). Furthermore, I am able to compile, in Quartus, the HDL pre-generated from the Qsys system by TerasIC and to program my C5G board; if the IP license was the problem, wouldn't there be an error at the compilation step as well, then?

    When generating the HDL, the line following the error messages is 

    Info: s0: "mem_if_lpddr2_emif_0" instantiated altera_mem_if_lpddr2_qseq "s0"

    Which implies that the error doesn't come from the lpddr2 sdram controller itself but from an internal subsystem (before trying to generate this "altera_mem_if_lpddr2_qseq", Qsys generates successfully a PLL used inside of the controller!).

    --- Quote Start ---

    Try this: in Qsys, double-click the controller to open its parameter editor. Edit a setting and then put it back to its original value. Then try generating the system again.

    --- Quote End ---

    Thank you for your suggestion but this didn't work. I also tried generating a Qsys system with the lpddr2 sdram controller alone (exporting all of its signals) and got exactly the same error.

    Let's say the problem is the IP license or, in general, is so that I am unable to use the lpddr2 sdram controller, what solutions do I then have for using the Micron MT42L128M32D1 that is on my C5G board? Except from buying the license and writing my own controller ...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Just to rule out licensing, which I don't really think it is, you can install Quartus Prime Standard Edition and run it for 30 days, including the IP base suite. You could also install the older version that the design was created and originally compiled with so you don't have to recompile it.

    That is really weird that a system with just the controller in it gave you the same error. I'm not sure what else to try.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    It's not a licensing problem, Quartus Lite handles it fine.

    @pctosi: Since you've been successful at just compiling the demo design, try as a next step upgrading the IP. You should see a notice and a button somewhere in the GUI (maybe it was in the project window, can't remember). The C5G demo was done in Quartus 13.1, IIRC. And just in case, are you sure you've installed the NIOS SDK (whatever it was called)?

    It might boil down to environment settings. Try "set" in a CMD prompt.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    It's not a licensing problem, Quartus Lite handles it fine.

    --- Quote End ---

    Great!

    --- Quote Start ---

    The C5G demo was done in Quartus 13.1, IIRC.

    --- Quote End ---

    This is correct.

    --- Quote Start ---

    And just in case, are you sure you've installed the NIOS SDK (whatever it was called)?

    --- Quote End ---

    As I was able to compile and load onto the FPGA projects including a Nios II and then to program the CPU using "Eclipse for Nios II" and as I have the Nios II CMD prompt installed, I would say yes.

    --- Quote Start ---

    Try as a next step upgrading the IP.

    --- Quote End ---

    I tried this and got a relatively similar error: 

    
Error: s0: Cannot find sequencer
Error: s0: An error occurred
    while executing
"error "An error occurred""
    (procedure "_error" line 8)
    invoked from within
"_error "Cannot find $seq_file""
    ("if" then script line 2)
    invoked from within
"if { == 0} {
        _error "Cannot find $seq_file"
    }"
    (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
    invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage ]"
    ("if" then script line 2)
    invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
        set calc_mem_size  > 0} {
        set seq_mem_size "
    (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
    invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "LPDDR2" $tmpdir QUARTUS_SYNTH"
    invoked from within
"foreach generated_file  {
        set file_name [file tail $gene..."
    (procedure "generate_synth" line 8)
    invoked from within
"generate_synth C5G_QSYS_mem_if_lpddr2_emif_s0"

    --- Quote Start ---

    It might boil down to environment settings. Try "set" in a CMD prompt.

    --- Quote End ---

    I'm pretty sure that's where the error comes from. The solution I linked to in my first post states

    --- Quote Start ---

    Description

    You may experience the above error when generating a UniPHY-based memory controller. The error occurs because one of the system environment variables 'TEMP' points to a network drive and not a local drive.

    Workaround/Fix

    The workaround is to point the TEMP variable to the local machine, such as the C: drive. Also the variable HOMEDRIVE should point to the local machine.

    --- Quote End ---

    and set gives 

    
HOMEDRIVE=C:
TEMP=C:\Users\<pctosi>\AppData\Local\Temp
TMP=C:\Users\<pctosi>\AppData\Local\Temp

    So what should I look for?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    I'm getting the same error and this seems to be a Windows 10 issue for Quartus versions 14 and above.

    I tried the following:

    Windows 10:

    13.0 OK

    13.1 Failed (pctosi) (https://alteraforum.com/forum/showthread.php?t=54838&p=225105#post225105)

    14.1 Failed

    15.0 Failed

    16.0 Failed

    Windows 7:

    16.1 OK (pctosi) (https://alteraforum.com/forum/showthread.php?t=54838&p=225105#post225105)

    Ubuntu

    15.0 OK

    All of these tests were using the same license and exact same Qsys design.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    I'm getting the same error and this seems to be a Windows 10 issue for Quartus versions 14 and above.

    --- Quote End ---

    I also had this issue with 13.1 (under Windows 10).

    I ended up using a Windows 7 VM with 16.1 to generate the HDL with Qsys. It's probably overkill but at least, it works and I'm not wasting time on this any more.