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So you're getting this error when you try to generate the system in Qsys?
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Yes.
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It looks like you're using the Lite version of Quartus Prime which does not include a license to the IP Base Suite which includes the memory controller IP (
https://www.altera.com/products/intellectual-property/design/ip-base-suite.html).
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Indeed, I am. If this is the reason, shouldn't I receive a clearer error message? (e.g. when using the
sdram controller, I receive the message "
sdram controller will only be supported in quartus prime standard edition in the future release"). Furthermore, I am able to compile, in Quartus, the HDL pre-generated from the Qsys system by TerasIC and to program my C5G board; if the IP license was the problem, wouldn't there be an error at the compilation step as well, then?
When generating the HDL, the line following the error messages is
Info: s0: "mem_if_lpddr2_emif_0" instantiated altera_mem_if_lpddr2_qseq "s0"
Which implies that the error doesn't come from the
lpddr2 sdram controller itself but from an internal subsystem (before trying to generate this "altera_mem_if_lpddr2_qseq", Qsys generates successfully a PLL used inside of the controller!).
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Try this: in Qsys, double-click the controller to open its parameter editor. Edit a setting and then put it back to its original value. Then try generating the system again.
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Thank you for your suggestion but this didn't work. I also tried generating a Qsys system with the
lpddr2 sdram controller alone (exporting all of its signals) and got exactly the same error.
Let's say the problem is the IP license or, in general, is so that I am unable to use the
lpddr2 sdram controller, what solutions do I then have for using the Micron MT42L128M32D1 that is on my C5G board? Except from buying the license and writing my own controller ...
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