Altera_Forum
Honored Contributor
12 years agoQsys instance parameters in generated verilog
I have a Qsys project, where I have added a couple parameters in the "Instance Parameters" tab. Using the 'instance script', I can ensure that these parameters are propagated to my instances. However, when I generate the top-level Verilog for my Qsys system, the instance parameters do not show up as verilog parameters.
According to the documentation: --- Quote Start --- The instance parameters tab in Qsys allows you to create instance parameters that enable instances of a Qsys system to be configured when the instances are added to other Qsys systems --- Quote End --- So, my Qsys system parameters can be configured by a parent Qsys system, but what about by a parent HDL module in Quartus? Is this not possible? Is there no way for Qsys to generate a parameterizable module for use in parent HDL modules? Thanks!