Qsys instance parameters in generated verilog

Actually, I just realized why this would not be feasible.

Let's say you actually could "export" your Qsys instance parameters in order to alter them when instantiating your top-level Qsys system. Now if any of your sub-components in your Qsys system which are also driven with those Qsys instance parameters (via the instance script) use those parameters to define port widths, it would be impossible for the Qsys Generator to generate code other than with what the instance parameter defaults are. You would basically have to be able to hook up your top level instance before you generate it - which of course is impossible.