Qsys instance parameters in generated verilog

--- Quote Start ---

I have a Qsys project, where I have added a couple parameters in the "Instance Parameters" tab. Using the 'instance script', I can ensure that these parameters are propagated to my instances. However, when I generate the top-level Verilog for my Qsys system, the instance parameters do not show up as verilog parameters.

According to the documentation:

So, my Qsys system parameters can be configured by a parent Qsys system, but what about by a parent HDL module in Quartus? Is this not possible? Is there no way for Qsys to generate a parameterizable module for use in parent HDL modules?

Thanks!

--- Quote End ---

I have the same question, but I see nobody answered this yet. Is it possible to have your Qsys Instance Parameters show up in the generated top-level Verilog wrapper as module instance parameters? I already define my parameters outside of Qsys and would like to feed them into my Qsys instance without having to redefine them in the Qsys GUI.