Qsys generation get stuck

Hi everyone,

I have a problem generating a qsys core.

I'm using the Quartus 12.1 SP1 suite and when I try to generate the QSYS core the environment goes stuck on the line:

Info: rio: exec C:/altera/12.1sp1/quartus/../ip/altera/common/ip_toolbench/v1.3.0/bin/ip_toolbench.exe -n {-devicefamily:Stratix IV} -lib_dir:C:/altera/12.1sp1/quartus/../ip/altera/rapidio/lib -flow_dir:C:/altera/12.1sp1/quartus/../ip/altera/common/ip_toolbench/v1.3.0/bin -wizard:rapidio -silent -parameterization.p_serial:1 -parameterization.p_xgmii:0 -parameterization.p_VOD:2 -parameterization.mode_selection:SERIAL_1X -parameterization.phy_selection:stratixivgx -parameterization.p_SYNC_ACKID:0 -parameterization.p_SEND_RESET_DEVICE:1 -parameterization.p_LINK_REQUEST_ATTEMPTS:7 -parameterization.p_data_rate:2500 -parameterization.p_ref_clk_freq:125 -parameterization.p_RXBUFRSIZE:4 -parameterization.p_TXBUFRSIZE:8 -parameterization.auto_cfg_rx:1 -parameterization.p_rx_threshold_0:20 -parameterization.p_rx_threshold_1:15 -parameterization.p_rx_threshold_2:10 -parameterization.p_TRANSPORT:1 -parameterization.p_TRANSPORT_LARGE:1 -parameterization.p_GENERIC_LOGICAL:0 -parameterization.p_PROMISCUOUS:1 -parameterization.rio_p_maintenance_master_slave:NONE -parameterization.p_MAINTENANCE_WINDOWS:1 -parameterization.p_TX_PORT_WRITE:0 -parameterization.p_RX_PORT_WRITE:0 -parameterization.rio_p_io_master_slave:AVALONMASTERSLAVE -parameterization.p_IO_SLAVE_WIDTH:29 -parameterization.p_READ_WRITE_ORDER:0 -parameterization.p_IO_MASTER_WINDOWS:1 -parameterization.p_IO_SLAVE_WINDOWS:1 -parameterization.p_DRBELL_TX:0 -parameterization.p_DRBELL_RX:0 -parameterization.p_DRBELL_WRITE_ORDER:0 -parameterization.p_DEVICE_ID:0x0 -parameterization.p_DEVICE_VENDOR_ID:0x0 -parameterization.p_DEVICE_REV:0xffffffff -parameterization.p_ASSEMBLY_ID:0x0 -parameterization.p_ASSEMBLY_VENDOR_ID:0x0 -parameterization.p_ASSEMBLY_REVISION:0x0 -parameterization.p_FIRST_EF_PTR:0x100 -parameterization.p_BRIDGE:0 -parameterization.p_MEMORY:1 -parameterization.p_PROCESSOR:0 -parameterization.p_SWITCH:0 -parameterization.p_PORT_TOTAL:1 -parameterization.p_PORT_NUMBER:0 -parameterization.p_SOURCE_OPERATION_DATA_MESSAGE:0 -parameterization.p_DESTINATION_OPERATION_DATA_MESSAGE:0 -parameterization.p_x4_mode:0 -parameterization.p_IO_MASTER:1 -parameterization.p_IO_SLAVE:1 -parameterization.p_MAINTENANCE:0 -parameterization.p_MAINTENANCE_MASTER:0 -parameterization.p_MAINTENANCE_SLAVE:0 -parameterization.p_ADAT:32 -parameterization.p_UNDER_SOPC:0 -parameterization.p_IO_SLAVE_OUTSTANDING_NREADS:16 -parameterization.p_IO_SLAVE_OUTSTANDING_NWRITE_RS:8 -simgen_enable.language:verilog -simgen_enable.enabled:0 -parameterization.p_UNDER_QSYS:1 C:/Users/Giacomo/AppData/Local/Temp/alt7981_5817592242511903221.dir/0001_rio_gen//QSYS_CORE_rio.v

The implemented Qsys module includes the following IPs:

• PCI express IP
• Rapid IO IP

The generation is stalled and I can only terminate by task manager.

Does anyone know why and if there is a workaround about it?

Thank you all.