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Altera_Forum's avatar
Altera_Forum
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10 years ago

QSys Error on custom IP ST connection

Hi, I am quite new to QSYS, I started using at September and I got some result.

On Linux PLL cannot be edited and don't save so I open XML file and I set manually parameter.

I sat down do after some time I learned a lot of feature and odds on QSYS, ALTPLL on Linux never got saved and I learned how to customize and check problem from XML source.

I also recently attended DECA forum goal of learning how to build a custom module but I was left alone without answer....

So after reading another tons of manuals I learned how to build a module, I ported about ten VHDL modules and I experimented how to interconnect them, some doubt are still remaining and I hit an issue is locking at an odd error:

I made a simple color translator from a 16bit stream to RGB stream and it doesn't connect to another module.

Here is module source and also some screen shoot of Quartus screen.

System data:

Linux Mint 17.2

8GB ram

Intel I7 on sony vaio laptop

Quartus 15.0 patch applied

here some screen shoot, I am grateful if someone can help me and other can suffer similar trouble point where it is.

Edit post: Disconnecting the offending node IP get generated and module appear as working less than connection.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Could you post some higher res screenshots? The attached images are only 400px x 200px, so it is impossible to see anything in them.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    Could you post some higher res screenshots? The attached images are only 400px x 200px, so it is impossible to see anything in them.

    --- Quote End ---

    Hi, thank for kind and prompt reply, images where attached as files but forum code I see resized them, I try with image embedding only of large one, the smallest I think are readable.

    I forgot on preceding post target board is BEmicro MAX10 with an attached RGB TFT parallel LCD

    http://www.alteraforum.com/forum/attachment.php?attachmentid=11631&stc=1

    Ok brute force against forum... Zipped file contain original images. How can I insert hi resolution on post?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The error is quite clearly explained. The Avalon-ST source has a symbol width of 16bits, but the sink has a symbol width of 8bits.

    Although your data buses are both 16bits, the symbols are organised differently. Essentially on the source you have a symbol width of 16bit, and one symbol per beat. The sink has a symbol width of 8bits and two symbols per beat (8x2=16bit).

    What properties did you set in your .tcl file for the custom component?

    As an example, in your design, I am guessing the following properties are set on the source interface: 

    
set_interface_property name dataBitsPerSymbol 16
set_interface_property name symbolsPerBeat 1

    And these two on the sink interface: 

    
set_interface_property name dataBitsPerSymbol 8
set_interface_property name symbolsPerBeat 2

    You can change one of the components so that they both match - this won't affect the compiled code as the bus will still be 16 bits wide, it just affects how Qsys interprets the interface.

    If the symbols of the source really are 16bits and the sink are really 8 bits, you should probably leave those settings as is (for future reference). What you can do instead is to make an adapter block with a sink input and source output with the two settings which would go in between - the HDL for it would be just the sink and source directly connected with no other logic.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    The error is quite clearly explained. The Avalon-ST source has a symbol width of 16bits, but the sink has a symbol width of 8bits.

    And these two on the sink interface: 

    
set_interface_property name dataBitsPerSymbol 8
set_interface_property name symbolsPerBeat 2

    You can change one of the components so that they both match - this won't affect the compiled code as the bus will still be 16 bits wide, it just affects how Qsys interprets the interface.

    --- Quote End ---

    Hi, thank a lot, yes this was the issue where coming for, on preceding test I generated some module and when interconnected together probably the same bit per symbol property matched the unit.

    I found on tcl source file and on graphical tool it was hidden. I need to grasp what signify this but for now it is enough to know how to fine tune interface.

    symbol per beat was not present nor in the tcl file nor in the graphical than on dual fifo, for the 24bit path I also adjusted bit per symbol to 24.

    Quartus manual is very large and also change with every release, I fear 15.1 is again different and new issue can appear so for now I try learn more before to install it.

    Code is working now I need fill memory from NIOS code to test for synk and modules behaviour.