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The error is quite clearly explained. The Avalon-ST source has a symbol width of 16bits, but the sink has a symbol width of 8bits.
And these two on the sink interface:
set_interface_property name dataBitsPerSymbol 8
set_interface_property name symbolsPerBeat 2
You can change one of the components so that they both match - this won't affect the compiled code as the bus will still be 16 bits wide, it just affects how Qsys interprets the interface.
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Hi, thank a lot, yes this was the issue where coming for, on preceding test I generated some module and when interconnected together probably the same bit per symbol property matched the unit.
I found on tcl source file and on graphical tool it was hidden. I need to grasp what signify this but for now it is enough to know how to fine tune interface.
symbol per beat was not present nor in the tcl file nor in the graphical than on dual fifo, for the 24bit path I also adjusted bit per symbol to 24.
Quartus manual is very large and also change with every release, I fear 15.1 is again different and new issue can appear so for now I try learn more before to install it.
Code is working now I need fill memory from NIOS code to test for synk and modules behaviour.
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