QSys Error on custom IP ST connection

The error is quite clearly explained. The Avalon-ST source has a symbol width of 16bits, but the sink has a symbol width of 8bits.

Although your data buses are both 16bits, the symbols are organised differently. Essentially on the source you have a symbol width of 16bit, and one symbol per beat. The sink has a symbol width of 8bits and two symbols per beat (8x2=16bit).

What properties did you set in your .tcl file for the custom component?

As an example, in your design, I am guessing the following properties are set on the source interface:

set_interface_property name dataBitsPerSymbol 16
set_interface_property name symbolsPerBeat 1

And these two on the sink interface:

set_interface_property name dataBitsPerSymbol 8
set_interface_property name symbolsPerBeat 2

You can change one of the components so that they both match - this won't affect the compiled code as the bus will still be 16 bits wide, it just affects how Qsys interprets the interface.

If the symbols of the source really are 16bits and the sink are really 8 bits, you should probably leave those settings as is (for future reference). What you can do instead is to make an adapter block with a sink input and source output with the two settings which would go in between - the HDL for it would be just the sink and source directly connected with no other logic.