QSYS BFM Simulation VHDL Help

Note how your VHDL code gets compiled into a library that has the same name as the component instance. I find this a terrible feature of Qsys. If I create ADC code, and an ADC package, and then compile it into an ADC library, then my VHDL would have the lines

library adc;

use adc.adc_pkg.all;

In Qsys there is no easy way to specific the library in which to compile your ADC, i.e., there is no way to over-ride the -work argument it uses to the vcom command. The BFM tutorial appendix "complains" about this :)

The _hw.tcl script should have a section for QUARTUS_SYNTH, VHDL_SIM, and VERILOG_SIM which lists of files to use during simulation. There is also a flag that can be used to allow mixed-mode simulation.

If none of this makes sense, perhaps post your project code to this thread, or to me directly (to my forum name) and I'll try to take a look.

Cheers,

Dave