QSYS BFM Simulation VHDL Help

Hi Dave,

Thanks for replying about this. I am still having problems. I had a look at the msim_setup.tcl and it looks like the correct files are being compiled when I run the script. I also see them in a library in the modelsim window.

I attempted to compile the library as you stated with vlib vmap and vcom but the not bound warnings persist when I run the elab.

I have attached the msim_setup.tcl that was generated (with extension txt or it wouldnt upload), in the com function (line 173 and 174) there are vcom's for both adc files.

  vcom     "$QSYS_SIMDIR/submodules/adc_sample.vhd"                                                                                                      -work adc_sample               
  vcom     "$QSYS_SIMDIR/submodules/adc_qsys.vhd"                                                                                                        -work adc_qsys     

Are these incorrect?

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your ADC _hw.tcl components need to define the files required for simulation as well as synthesis.

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Do I need to edit or include the *hw.tcl files somehow?

To add to the confusion I noted in the component editor in qsys under files there is a VHDL Simulation Files window, do I need to have something in here? I have tried using the same file as the synthesis (there is a copy from synthesis files button) but this generates a warning the SIM_VHDL fileset must specify the top-level module name. There is also a simulation section in the qsys generate, do I need to use this? In the tutorial this wasnt required so im guessing I dont need to worry about either of these?