QSYS BFM Simulation VHDL Help

When you simulate your Qsys system, all the files needed for simulation should ideally appear in msim_setup.tcl, eg., your ADC _hw.tcl components need to define the files required for simulation as well as synthesis.

Quartus Qsys is a little annoying when it comes to getting all the simulation files correct. I'll often use my own pre-compiled libraries for components. In your case, just compile the missing components, eg., create the library and compile your ADC source

vlib adc_qsys

vmap adc_qsys ./adc_qsys

vcom -2008 -work adc_qsys <adc VHDL filename>

Once you eliminate the warnings about missing components, your simulation should run. At that point you could write your own sim.tcl script that calls msim_setup.tcl and compiles the stuff that Quartus misses.

Cheers,

Dave